1. Field of the Invention
The present invention relates to an arbitration mechanism for controlling access to a buffer provided as part of a storage device. More specifically, the present invention relates to a hard disk buffer arbitration subsystem.
2. Description of Background Information
Computer systems (e.g., personal computers, workstations and the like) and intelligent devices (e.g., appliances, kiosks, consumer electronic devices provided with microcontrollers and microprocessors) are typically provided with memory systems having memory hierarchies for handling the computer system""s long-term and short-term storage needs. Such memory hierarchies comprise primary (main) storage devices such as the computer""s main memory (typically random access memory (RAM)) and secondary (auxiliary) storage devices such as disk drives (typically magnetic hard disks) and other external devices. The memory system manages the exchange of data between the main memory and the auxiliary memory, and thereby enhances the computer""s perceived performance. One such management function includes cachingxe2x80x94keeping active data in the memory having a higher access speed, i.e., in the main memory. As the data becomes inactive, it is migrated to the lower-speed auxiliary memory. Another function of the memory system involves buffering of data transferred to and from the auxiliary memory. For this purpose, a buffer having a buffer channel with a relatively high data transfer rate is provided. The buffer may be provided as part of the computer, or it may be provided within the storage device containing the auxiliary memory, such as is the case with disk drives with built-in disk buffers, dedicated to disk operations.
The time it takes to access a disk device is substantial in comparison to accessing the primary/main memory. Time is needed for a read/write head to position itself over the track that contains the stored data. It takes more time to rotate the media until the read/write head reaches the stored data. Another delay is encountered in transmitting the data from the auxiliary memory through an input/output port to the main memory. Not only is there a delay due to the transfer rate limitations of the input/output port, but the requester may be temporarily denied access to the input/output port in favor of another requester already using the input/output port.
Disk buffers can alleviate the perceived access delays of the disk device by buffering data in fast memory without burdening the input/output channel feeding to the actual disk media. The disk buffer may also concurrently serve as a cache, accessing and holding disk data not yet but likely to be requested.
The computer system may have clients, e.g., an application and various processes provided within the disk drive, which request access to the disk buffer. Such clients may make concurrent and thus contentious demands on the disk buffer""s channel which has a limited data transfer rate. Thus, schemes have been incorporated in disk drives to arbitrate between the various disk buffer access requests. Traditionally, such schemes have included either a fixed priority encoder or a xe2x80x9cround-robinxe2x80x9d scheme. A fixed priority encoder scheme assigns a fixed request level to each client. A given requestor will gain access to the buffer when two conditions are satisfied. The buffer must not be already is use, and there must be no higher priority client also requesting access to the buffer. In the case of a xe2x80x9cround-robinxe2x80x9d scheme, each time the buffer finishes an operation, it will circulate from client to client polling for a requester. If a client is requesting at the time it is polled, it will gain access to the buffer. Otherwise, the client must wait for the next occurrence of its poll in the round-robin queue.
Difficulties associated with these approaches are that they assume relatively static requirements such as latency limits and memory bandwidth requirements. This is not always the case with disk drive environments.
There is a need for an arbitration mechanism which will limit the latency associated with buffer access requests for select clients such as disk and micro-instruction buffer accesses during heavy load intervals, but will continue to give priority access to other clients as the load diminishes. The system would be preferably versatile and programmable to allow the varying of priorities assigned to certain clients when vying for access to the buffer.
3. Definitions of Terms
In a computer system, a process by which a process, device, or subsystem receives requests for access to a single resource, for example, a channel, and decides which one of the requesters will get access.
A path or link through which information passes between two devices, subsystems, or units. A channel can be internal and/or external to a computer, and has a limited bandwidth (i.e., rate of data transfer, in bits per second).
A process, which may be performed by a program, task, device, or circuitry, which requests a service provided by another process.
In a computer system, a process by which two or more devices, entities, or processes vie for access to a single resource, for example, a channel.
The movement of data from one location to another.
The delay between a request for a data transfer action (involving movement of data from one location to another) and the time the action is performed. When the data transfer is a request for information, the latency is the time from the making of the request to the time the information is supplied to the requester.
The present invention is provided to improve upon subsystems for arbitrating requests for access to a storage device buffer, by allocating the use of a buffer channel in a manner so as to best accommodate the functionality of the overall computer system and its application. In order to achieve this end, one or more aspects of the present invention may be followed in order to bring about one or more specific objects and advantages, such as those noted below.
One object of the present invention is to provide an improved mechanism for storage device buffer arbitration which limits the latency associated with a buffer access request from select clients.
The present invention, therefore, may be directed to a memory method or system, or one or more parts thereof, for use in a system having a host computer comprising an application and an operating system, or for use in an intelligent device such as an appliance having a microcontroller. Such a computer subsystem or intelligent device may comprise a disk storage device such as a magnetic hard disk storage device.
In accordance with one aspect of the present invention, a memory subsystem is provided. The memory subsystem comprises a buffer, a storage device, a buffer access determining mechanism, a request communicator, and a disk input/output subsystem. The buffer has a limited storage capacity and comprises a buffer channel having a limited data transfer rate. The storage device comprises a read/write mechanism and non-volatile storage media. The buffer access determining mechanism determines when a given client is to be given access to the buffer channel. The buffer access determining mechanism comprises a latency monitor for monitoring a latency parameter indicative of buffer channel access latency for the given client, and further comprises a buffer access controller for controlling when the given client is given access to the buffer channel in accordance with the monitored latency parameter.
The request communicator couples requestors to the buffer access determining mechanism. The requestors request the buffer access determining mechanism to give clients access to the buffer channel. When they are given access to the buffer channel, the clients write data to or read data from the buffer via the buffer channel. The disk input/output subsystem exchanges data between the buffer and the storage media.
The memory subsystem may be a disk storage memory subsystem, having a translating component for receiving memory access requests from an external process of a host computer or microcontroller and translating the memory access requests to memory access requests corresponding to actual addresses located in the buffer. More specifically, the memory subsystem may be a peripheral hard disk device. The buffer may comprise a volatile high speed transfer rate memory, such as a random access memory. The storage device may comprise a non-volatile memory having a lower transfer rate, such as a disk storage device (e.g., a magnetic hard disk storage device). The buffer access determining mechanism may comprise an arbitrator.
The latency monitor may comprise a setting register, a counter, and a high latency signaller. The setting register holds a value representing a threshold delay in granting a given client access to the buffer. The counter counts an amount of time elapsing from a reset time. The reset time may be the last time the given client was granted access, or the time at which the given client requests access to the buffer. The high latency signaller signals to the buffer access controller when the threshold delay has been reached by the counter. To render the latency monitor easily configurable, the setting register may be software programmable.
The buffer channel access controller may comprise a priority-based arbitrator which assigns to an access request from the given client a default priority when the threshold delay has not been reached by the counter, and a higher priority when the threshold delay has been reached by the counter. The priority-based arbitrator may comprise a fixed-priority encoder.
In accordance with another aspect of the present invention, a hard disk buffer arbitration subsystem may be provided which responds to client requests to provide, to a microprocessor or microcontroller, disk input/output processes, and hard disk control processes, access to the buffer. A latency monitor is provided for monitoring a latency parameter indicative of the buffer access latency for a given client. A buffer access controller controls when the given client is given access to the buffer in accordance with the latency parameter. The buffer may comprise a random access memory.
The latency monitor may comprise a setting register, a counter, and a high latency signaller. The setting register holds a value representing a threshold delay in granting a given client access to the buffer. The counter counts an amount of time elapsing from a reset timexe2x80x94e.g., a time at which a buffer access request was last granted to the given client. The high latency signaller signals to the buffer access controller when the threshold delay has been reached by the counter. The setting register may be software programmable. The buffer channel access controller may comprise a priority-based arbitrator which assigns to an access request from the given client a default priority when the threshold delay has not been reached by the counter and a higher priority when the threshold delay has been reached by the counter. The priority-based arbitrator may comprise a fixed-priority encoder.